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ABRIDGED DATA SHEET
Rev 1; 4/09
1Kb I2C/SMBus EEPROM with SHA-1 Engine
General Description
The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The memory is organized as four 32-byte pages. Data copy protection and EPROM emulation features are supported for each memory page. Each DS28CN01 has a guaranteed unique factory-programmed 64-bit registration number. Communication with the DS28CN01 is accomplished through an industrystandard I 2 C-compatible and SMBusTM-compatible interface. The SMBus timeout feature resets the device's interface if a bus-timeout fault condition is detected.
Features
1024 Bits of EEPROM Memory Partitioned Into Four Pages of 256 Bits Dedicated Hardware-Accelerated SHA-1 Engine for Generating SHA-1 MACs EEPROM Memory Pages Can Be Individually Copy Protected or Put Into EPROM Mode (Program from 1 to 0 Only) Write Access Requires Knowledge of the Secret and the Capability of Computing and Transmitting a 160-Bit MAC as Authorization Unique, Factory-Programmed, and Tested 64-Bit Registration Number Assures Absolute Traceability Because No Two Parts are Alike Endurance 200,000 Cycles at +25C Serial Interface User Programmable for I2C Bus and SMBus Compatibility Supports 100kHz and 400kHz I2C Communication Speeds +5.5V Tolerant Interface Pins Operating Ranges: +1.62V to +5.5V, -40C to +85C 8-Pin SOP Package
DS28CN01
Applications
PCB Unique Serialization Accessory and Peripheral Identification Equipment Registration and License Management Network Node Identification Printer Cartridge Configuration and Monitoring Medical Sensor Authentication and Calibration System Intellectual Property Protection
Pin Configuration
PART
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 SOP 8 SOP DS28CN01U-A00+
TOP VIEW
AD0 AD1 N.C. GND 1 2 3 4
+
DS28CN01
8 7 6 5
VCC N.C. SCL SDA
DS28CN01U-A00+T
+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
SOP
Typical Operating Circuit appears at end of data sheet.
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine DS28CN01
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.........-0.5V to +6V Maximum Current on Any Pin ...........................................20mA Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40C to +85C.) (Note 1)
PARAMETER Supply Voltage Standby Current Operating Current Power-Up Wait Time EEPROM Programming Time Programming Current Endurance (Notes 3, 4, 5) Data Retention (Notes 6, 7, 8) SHA-1 ENGINE SHA-1 Computation Time SHA-1 Computation Current tCSHA ILCSHA See full version of the data sheet. See full version of the data sheet. 0.3 x VCC 0.25 x VCC VCCMAX + 0.3V VCCMAX + 0.3V ms mA t PROG I PROG NCY tDR VCC 2.0V 10 45 1.2 200,000 50,000 40 VCC < 2.0V VCC = +5.5V At +25C At +85C At +85C ms mA -- Years SYMBOL VCC ICCS ICCA t POIP Bus idle, VCC = +5.5V Bus active at 400kHz, VCC = +5.5V (Note 2) CONDITIONS MIN 1.62 TYP MAX 5.50 5.5 500 5 UNITS V A A s
SCL, SDA, AD1, AD0 PINS (Notes 9, 10) VCC Low-Level Input Voltage VIL VCC < 2.0V VCC High-Level Input Voltage VIH VCC < 2.0V VCC VHYS VCC < 2.0V Low-Level Output Voltage at 4mA Sink Current, Open Drain VCC VOL 2.0V 2.0V 2.0V -0.3 0.7 x VCC 0.8 x VCC 0.05 x VCC 0.1 x VCC 0.4 0.2 x VCC V 2.0V -0.3
V
V
Hysteresis of Schmitt Trigger Inputs (Note 2)
V
VCC < 2.0V
2
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ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40C to +85C.) (Note 1)
PARAMETER Output Fall Time from VIH(MIN) to VIL(MAX) with a Bus Capacitance from 10pF to 400pF (Notes 2, 11) Pulse Width of Spikes that are Suppressed by the Input Filter Input Current with an Input Voltage Between 0.1VCC and 0.9VCCMAX Input Capacitance SCL Clock Frequency Bus Timeout Hold-Time (Repeated) START Condition; After this Period, the First Clock Pulse is Generated Low Period of the SCL Clock (Note 14) High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time (Notes 15, 16) Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line SYMBOL VCC t OF VCC < 2.0V t SP (Note 2) 2.0V CONDITIONS MIN 20 + 0.1CB 20 + 0.1CB TYP MAX 250 ns 300 50 ns UNITS
DS28CN01
II CI f SCL tTIMEOUT tHD:STA
(Note 12) (Note 2) (Note 13) (Note 13) (Note 14) VCC 2.7V 2.0V
-10
+10 10 400
A pF kHz ms s
25 0.6 1.3 1.5 1.9 0.6 0.6 0.3 0.3 0.3 100 0.6 1.3
75
tLOW tHIGH t SU:STA
VCC
s s s 0.9 1.1 1.5 ns s s 400 pF s
VCC < 2.0V (Note 14) (Note 14) VCC tHD:DAT t SU:DAT t SU:STO tBUF CB VCC 2.7V 2.0V
VCC < 2.0V (Notes 2, 14, 17) (Note 14) (Note 14) (Notes 2, 14)
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
Specifications at -40C are guaranteed by design and characterization only and not production tested. Guaranteed by design, characterization, and/or simulation only and not production tested. This specification is valid for each 8-byte memory row. Write-cycle endurance is degraded as TA increases. Not 100% production tested; guaranteed by reliability monitor sampling. Data retention is degraded as TA increases. Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. Note 8: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125C or 40 years at +85C. Note 9: All values are referred to VIH(MIN) and VIL(MAX) levels. Note 10: See Figure 3. Note 11: CB = Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I2C Bus Specification v2.1 are allowed. _______________________________________________________________________________________ 3
ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine DS28CN01
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40C to +85C.) (Note 1) Note 12: The DS28CN01 does not obstruct the SDA and SCL lines if Vcc is switched off. Note 13: The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 and SCL stays at the same logic level or SDA stays low for this interval, the DS28CN01 behaves as though it has sensed a STOP condition. Note 14: System requirement. Note 15: The DS28CN01 provides a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 16: The master can provide a hold time of 0ns minimum when writing to the device. This 0ns minimum is guaranteed by design, characterization, and/or simulation only, and not production tested. Note 17: A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.
Pin Description
PIN 1 2 3, 7 4 5 6 8 NAME AD0 AD1 N.C. GND SDA SCL VCC FUNCTION Device Address Input Pin to Select the Slave Address. Sets slave address bits A[1:0] and must be connected to either GND, SDA, SCL, or VCC. Device Address Input Pin to Select the Slave Address. Sets slave address bits A[3:2] and must be connected to either GND, SDA, SCL, or VCC. No Connection Ground Supply I2C/SMBus Bidirectional Serial Data Line. This pin must be connected to VCC through a pullup resistor. I2C/SMBus Serial Clock Input. This pin must be connected to VCC through a pullup resistor. Power-Supply Input
Detailed Description
The DS28CN01 features a serial I2C/SMBus interface, 1Kb of SHA-1 secure EEPROM, a register page, and a unique registration number, as shown in the Block Diagram. The device communicates with a host processor through its I2C interface in standard mode or in fast mode. The user can switch the interface from I2C bus mode to SMBus mode. Two 4-level address pins allow 16 DS28CN01s to reside on the same bus segment.
Serial Communication Interface
The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector output to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the standard mode, and up to 400kbps in the fast mode. The DS28CN01 works in both modes. A device that sends data on the bus is defined as a transmitter and a device receiving data is a receiver. The device that controls the communication is called a master. The devices that are controlled by the master are slaves. The DS28CN01 is a slave device.
Device Operation
Read and write access to the DS28CN01 is controlled through the I 2 C/SMBus serial interface. Since the DS28CN01 has memory areas and registers of different characteristics, there are several special cases to consider. See the Read and Write section in the full data sheet for details.
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ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine
Block Diagram
VCC AD_ SCL SDA I2C/SMBUS FUNCTION CONTROL MEMORY AND SHA-1 ENGINE CONTROL
DS28CN01
MAC OUTPUT BUFFER 64-BIT UNIQUE NUMBER
MAC COMPARATOR
SHA-1 ENGINE
8-BYTE WRITE BUFFER
SECRET MEMORY
REGISTER PAGE
DS28CN01
USER EEPROM 4 PAGES OF 32 BYTES
Slave Address/Direction Byte
To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus. The slave address to which the DS28CN01 responds is shown in Figure 1. The slave address is part of the slave-address/direction byte. The upper 3 bits of the DS28CN01 slave address are set to 101b. The AD0 pin controls address A0 and A1; AD1 controls A2 and A3. AD0 and AD1 can be connected to GND,
VCC, SCL, or SDA. Table 1 shows the translation of these four pin states to binary addresses. To be selected, the device must be addressed with A0 to A3 matching the binary address of the respective pins. The last bit of the slave-address/direction byte (R/W) defines the data direction. When set to a 0, subsequent data flows from master to slave (write-access mode); when set to a 1, data flows from slave to master (readaccess mode).
Table 1. Pin State to Binary Translation
7-BIT SLAVE ADDRESS
AD1
A6 1 A5 0 A4 1 A3 AD1 A2 A1 AD0 A0 R/W
A3 0 0 1 1
A2 0 1 0 1
AD0 GND VCC SCL SDA
A1 0 0 1 1
A0 0 1 0 1
GND VCC SCL SDA
MSB
4-LEVEL PIN STATES (SEE THE SLAVE DETERMINES ADDRESS/DIRECTION READ OR WRITE BYTE SECTION)
Figure 1. Slave Address
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ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine DS28CN01
MSB FIRST SDA MSB LSB MSB LSB
SLAVE ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/ NACK
SCL
1-7
8
9
1-7
8
9
1-7
8
9
IDLE
START CONDITION
REPEATED IF MORE BYTES ARE TRANSFERRED
STOP CONDITION REPEATED START
Figure 2. I2C/SMBus Protocol Overview
I2C/SMBus Protocol
Data transfers can be initiated only when the bus is not busy. The master generates the SCL, controls the bus access, generates the START and STOP conditions, and determines the number of bytes transferred on the SDA line between START and STOP. Data is transferred in bytes with the most significant bit being transmitted first. After each byte, an acknowledge bit follows to allow synchronization between master and slave. During any data transfer, SDA must remain stable whenever the clock line is high. Changes in the SDA line while SCL is high are interpreted as a START or a STOP. The protocol is illustrated in Figure 2. See Figure 3 for detailed timing references. Bus Idle or Not Busy Both SDA and SCL are inactive, i.e., in their logic-high states. START Condition To initiate communication with a slave, the master must generate a START condition. A START condition is defined as a change in state of SDA from high to low while SCL remains high. STOP Condition To end communication with a slave the master must generate a STOP condition. A STOP condition is defined as a change in state of SDA from low to high while SCL remains high.
Repeated START Condition Repeated STARTs are commonly used for read accesses after having specified a memory address to read from in a preceding write access. The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal START condition, but without a preceding STOP condition. Data Valid With the exception of the START and STOP condition, transitions of SDA can occur only during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold time (tHD:DAT after the falling edge of SCL and t SU:DAT before the rising edge of SCL; see Figure 3). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL pulse. When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT + tR in Figure 3) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
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ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine DS28CN01
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C/SMBus Timing Diagram
Acknowledged by Slave A slave device, when addressed, is usually obliged to generate an acknowledge after the receipt of each byte. The master must generate the clock pulse for each acknowledge bit. A slave that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. Setup and hold times tSU:DAT and tHD:DAT must be taken into account. Acknowledged by Master To continue reading from a slave, the master is obliged to generate an acknowledge after the receipt of each byte. The master must generate the clock pulse for each acknowledge bit. A master that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. Setup and hold times tSU:DAT and tHD:DAT must be taken into account. Not Acknowledged by Slave A slave device may be unable to receive or transmit data either because of an invalid access mode, because the SHA-1 engine is running, or because a
EEPROM write cycle is in progress. In this case, the DS28CN01 does not acknowledge any bytes that it refuses by leaving SDA high during the high period of the acknowledge-related clock pulse. See the Read and Write section in the full data sheet for a detailed list of situations where the DS28CN01 does not acknowledge. Not Acknowledged by Master At some time when receiving data, the master must terminate a read access. To achieve this, the master does not acknowledge the last byte that it has received from the slave by leaving SDA high during the high period of the acknowledge-related clock pulse. In response, the slave stops transmitting, allowing the master to generate a STOP condition.
Data Memory and Registers
For this section including Figures 4 and 5 and Table 2, refer to the full version of the data sheet. Read and Write This section discusses the read and write behavior of the EEPROM and the various registers. Refer to the full data sheet for details, including Tables 3 to 13.
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ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine DS28CN01
SHA-1 Computation Algorithm
This description of the SHA-1 computation is adapted from the Secure Hash Standard SHA-1 document that can be downloaded from the NIST website. Refer to the full version of the data sheet for more details. value for the pullup resistor is 1.275k. The "Minimum RP" line in Figure 6 shows how the minimum pullup resistor changes with the operating (pullup) voltage. For I2C systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum bus capacitance CB is 400pF. The maximum rise time must not exceed 300ns. Assuming maximum rise time, the maximum resistor value at any given capacitance C B is calculated as: R PMAX = 300ns/(C B x ln(7/3)). For a bus capacitance of 400pF the maximum pullup resistor would be 885. Since an 885 pullup resistor, as would be required to meet the rise time specification and 400pF bus capacitance, is lower than R PMIN at +5.5V, a different approach is necessary. The "Maximum Load" line in Figure 6 is generated by first calculating the minimum pullup resistor at any given operating voltage ("Minimum RP" line) and then calculating the respective bus capacitance that yields a rise time of 300ns. Only for pullup voltages of +4V and lower can the maximum permissible bus capacitance of 400pF be maintained. A reduced bus capacitance of 300pF is acceptable for the entire operating voltage range. The corresponding pullup resistor value at the voltage is indicated by the "Minimum RP" line.
Applications Information
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS28CN01 that requires a pullup resistor (see the Typical Operating Circuit) to realize high logic levels. Because the DS28CN01 uses SCL only as input (no clock stretching), the master can drive SCL either through an opendrain/collector output with a pullup resistor or a push-pull output.
Pullup Resistor RP Sizing According to the I2C specification, a slave device must be able to sink at least 3mA at a VOL of +0.4V. The SMBus specification requires a current sink capability of 4mA at +0.4V. The DS28CN01 can sink at least 4mA at +0.4V VOL over its entire operating voltage range. This DC characteristic determines the minimum value of the pullup resistor: RPMIN = (VCC - 0.4V)/4mA. With a maximum operating voltage of +5.5V, the minimum
1200 1000 MINIMUM RP () 800 MINIMUM RP 600 MAXIMUM LOAD AT MINIMUM RP FAST MODE 400 200 0 1.5 2.0 2.5 3.0 3.5 PULLUP VOLTAGE (V) 4.0 4.5 5.0 5.5
600 500 400 300 200 100 0
Figure 6. I2C Fast-Speed Pullup-Resistor Selection Chart
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LOAD (pF)
ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine
Typical Operating Circuit
VCC RP VCC SDA SCL C VCC SDA SCL TO ADDITIONAL DEVICES RP
DS28CN01
GND AD0 AD1
DS28CN01
GND
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 8 SOP PACKAGE CODE U8+3 DOCUMENT NO. 21-0036
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ABRIDGED DATA SHEET
1Kb I2C/SMBus EEPROM with SHA-1 Engine DS28CN01
Revision History
REVISION NUMBER 0 1 REVISION DATE 6/07 4/09 Initial release. Created newer template-style data sheet. DESCRIPTION PAGES CHANGED -- All
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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